Implementing a highly-linear Voltage-to-time converter circuit for a low power 10-bit 200kS/s SAR ADC with Adaptive Conversion cycle for high-quality audio applications in 0.18um TSMC CMOS process technology

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dc.contributor.advisorAguilera-Galicia, Cuauhtémoc R.
dc.contributor.authorFigueroa-Vázquez, Cristian F.
dc.date.accessioned2020-10-14T01:25:59Z
dc.date.available2020-10-14T01:25:59Z
dc.date.issued2020-08
dc.descriptionThis document presents a 0.18 um CMOS process highly-linear Voltage-to-Time Converter (VTC) design that can operate at a low voltage of 1.8 V across PVT corners and with the power consumption of less than 13 uW and linearity error less than 1%. The VTC was designed to work at a minimum of 1.68 V and accepts a maximum clock frequency of 900 MHz; to reduce non-linear behavior a symmetric load and current starved inverter configuration was proposed. This circuit was designed using TSMC 0.18 um CMOS process technology.es_MX
dc.description.sponsorshipITESO, A. C.es
dc.identifier.citationFigueroa-Vázquez, C. F. (2020). Implementing a Highly-linear Voltage-to-time Converter Circuit for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Process Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESOes_MX
dc.identifier.urihttps://hdl.handle.net/11117/6366
dc.language.isoenges_MX
dc.publisherITESOes_MX
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdfes_MX
dc.subjectHigh-Quality Audioes_MX
dc.subjectVoltage to Time Converteres_MX
dc.subjectAnalog to Digital Converteres_MX
dc.titleImplementing a highly-linear Voltage-to-time converter circuit for a low power 10-bit 200kS/s SAR ADC with Adaptive Conversion cycle for high-quality audio applications in 0.18um TSMC CMOS process technologyes_MX
dc.typeinfo:eu-repo/semantics/academicSpecializationes_MX
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones_MX

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