Design and Integration of a Deserializer Module for a SerDes Mixed Signal System on Chip

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dc.contributor.authorCenteno-Quiñonez, José M.
dc.contributor.directorAguilera-Galicia, Cuauhtémoc R.
dc.contributor.directorGirón-Allende, Alexandro
dc.contributor.directorAvedaño-Fernández, Víctor
dc.date.accessioned2016-07-07T22:12:55Z
dc.date.available2016-07-07T22:12:55Z
dc.date.issued2015-12
dc.descriptionThis document presents a mixed signal System on Chip design developed at ITESO as a test vehicle for manufacturing at 180 nm node through MOSIS manufacturing services. The ITESO TV1 is a serializer and deserializer based on the PCIe protocol. The current report includes details on the design for the deserializer digital module for the SerDes. The testing done at RTL and gate level abstractions to the Deserializer are presented. The report finishes by discussing the VLSI technique used for the system integration of analog and digital modules in the SerDes. This research effort is a first attempt at ITESO to generate a mixed signal complex system for manufacturing.es
dc.description.sponsorshipConsejo Nacional de Ciencia y Tecnologíaes
dc.identifier.citationCenteno-Quiñonez, J. M. (2015). Design and Integration of a Deserializer Module for a SerDes Mixed Signal System on Chip. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.es
dc.identifier.urihttp://hdl.handle.net/11117/3750
dc.language.isoenges
dc.publisherITESOes
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes
dc.subjectSerDeses
dc.subjectDeserializeres
dc.subjectSoCes
dc.subject180 NMes
dc.subjectVLSIes
dc.titleDesign and Integration of a Deserializer Module for a SerDes Mixed Signal System on Chipes
dc.typeinfo:eu-repo/semantics/academicSpecializationes
rei.peerreviewedYeses

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