AI-Enhanced Post-Silicon Validation: Tackling Signal Integrity Issues in High-Speed Interconnects

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Miniatura

Fecha

2025-01-23

Autores

Rangel-Patiño, Francisco
Vega-Ochoa, Edgar A.
Viveros-Wacher, Andres
Onsongo, Daudi
Rayas-Sánchez, José E.

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Editor

IEEE

Resumen

Semiconductor technology advances, coupled with the demand for higher data rates and bandwidth, has led to significant signal integrity issues such as attenuation, crosstalk, jitter, noise, EM susceptibility, etc. Traditional post-silicon validation methods for high-performance computer platforms, which rely heavily on manual inspection and rule-based heuristics, are increasingly inadequate for addressing these complexities. In this paper, we review and highlight the application of artificial intelligence (AI) approaches and machine learning (ML) techniques to automate post-silicon validation and enhance the detection and diagnosis of signal integrity issues in high-speed computer interfaces. Through a series of case studies, we demonstrate the efficacy of various AI techniques, including artificial neural networks (ANNs), surrogate modeling, and unsupervised learning, in optimizing settings and improving the efficiency of post-silicon validation. These techniques significantly reduce the number of required measurements, enhance accuracy, and provide scalable and flexible solutions for modern post-silicon physical layer validation and tuning processes.

Descripción

Palabras clave

AI, ANNs, GPR, HSIO, ML, PCIe, SATA, Attenuation, Crosstalk, Equalization, High-speed Interconnects, Jitter, K-means Clustering, Noise, Optimization, Post-silicon Validation, Signal Integrity, Space Mapping, Surrogate Modeling, System Margining, Unsupervised Learning

Citación

F. E. Rangel-Patiño, E. A. Vega-Ochoa, A. Viveros-Wacher, D. Onsongo, and J. E. Rayas-Sanchez. AI-enhanced post-silicon validation: tackling signal integrity issues in high-speed interconnects, in IEEE MTT-S Latin America Microwave Conf. (LAMC-2025), San Juan, Puerto Rico, Jan. 2025, pp. 66-69.