DESI - Trabajos de fin de Maestría en Diseño Electrónico
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Ítem Diseño e implementación del curso de Fundamentos de microprocesadores y microcontroladores(ITESO, 2025-02) Sinsel-Duarte, Martín A.; Longoria-Gándara, Omar H.Esta tesis presenta el proceso de diseño e implementación del curso de Fundamentos de Microprocesadores y Microcontroladores que ofrece el Instituto Tecnológico y de Estudios Superiores de Occidente a partir de agosto de 2023. Este curso atiende a los procesos de mejora continua que requiere el Consejo de Acreditación de Enseñanza de la Ingeniería (CACEI), y se ofrece como curso obligatorio para las carreras de Ingeniería en Electrónica, Ingeniería en Sistemas Digitales Embebidos e Ingeniería en Mecatrónica. El proceso implicó una revisión del uso de los microcontroladores en la academia, a nivel licenciatura, y su vínculo con la industria. Así mismo se analizaron algunas de las estrategias didácticas utilizadas para enseñar estas tecnologías a nivel universitario. A lo largo del documento, se desglosa la propuesta del curso en los elementos constitutivos de la guía de aprendizaje, y se presentan los materiales didácticos elaborados, programas de ejemplo y las actividades de aprendizaje, orientados a lograr los objetivos del curso.Ítem Optimization of a TSPC D flip-flop using MatLab(ITESO, 2025-01) Martínez-Flores, Iván; Chávez-Hurtado, José L.The central focus of this case study is the simulation and optimization of a True Single Phase Clock (TSPC) D flip-flop using WinSpice for circuit simulation and MATLAB for optimization. The primary objective of this TOG is to minimize the setup time of the TSPC D flip-flop, thereby enabling faster input processing and improving overall circuit performance. This was achieved using the embedded codes in MATLAB, which included fminsearch, fmincon, and genetic algorithms. These algorithms were used to find the optimal transistor dimensions without requiring a manual implementation. A TSPC D flip-flop is a specialized version of a D flip-flop that operates with a single-phase clock throughout its design. It avoids using a negated clock signal that can introduce unwanted delays and timing issues. This characteristic makes it particularly suited for high-speed applications. Appendix A contains the complete codebase, including the scripts used for each function and their corresponding file names. This appendix ensures the reproducibility of the results and provides a detailed reference for future researchers seeking to replicate or extend this study.Ítem A Practical Start with Zephyr RTOS(ITESO, 2024-12) Ramírez-Sánchez, Earl O.; Longoria-Gándara, Omar H.; Pizano-Escalante, José L.The field of embedded systems has grown significantly in recent years, driving increased demand for advanced Real-Time Operating Systems (RTOS). These systems manage complex tasks, ensure fast responses, and optimize resource usage. Zephyr RTOS stands out as an open-source solution with solid community support and compatibility across various hardware platforms. Supported by the Linux Foundation, its modular design makes it an appealing choice for scalable and customizable solutions. However, new users often face challenges when configuring it for hardware that lacks native support, especially when working with Devicetree structures and Kconfig files. While powerful, these components require a solid understanding of system configuration and hardware integration. This case study provides a practical guide to reduce the learning curve and help developers adapt Zephyr to their projects. It covers critical topics such as adding hardware support for the NXP FRDM-K66F board and a Liquid Crystal Display (LCD) with the PCD8544 controller, handling interrupts, managing multithreading and synchronization, and integrating external devices.Ítem Machine Learning Algorithms for Small Datasets with Reinforcement Learning and Optimization(ITESO, 2024-10) Soule-Ascencio, Santiago; Gómez-Cortés, ArturoAs computers evolve and their computational complexity and performance increase, many forms of machine learning have found new implementations and applications to take advantage of these computer features. Previously, areas dominated exclusively by purpose-built software or fully manual applications have found newly developed innovation from Machine Learning development. Reinforcement Learning is a way to implement some algorithms that are being explored. Working in a similar way to teaching a young child to perform a task by giving positive or negative feedback depending on their actions, this form of machine learning has great potential with some disadvantages. The results can sometimes greatly outperform computational deterministic implementations. Being an unexplored area, this investigation has the purpose of implementing and comparing multiple machine learning algorithms with a reinforcement learning optimization algorithm to find out the advantages and disadvantages of each one. Most of the research involves a reinforcement learning Intel project that would benefit greatly from the results of this investigation and will also suggest that there are certain restrictions that the algorithm implementations must follow. It is also the goal of the investigation to find which algorithm is the most optimal for the Intel project mentioned. Benchmarking and thorough testing will be done with a real system and implementation of each algorithm to compare objective data during the investigation, as well as an analysis of advantages and harmful properties of each algorithm. Results will be published in the last sections of the document with as much detail as possible without giving confidential information from Intel’s intellectual property.Ítem Availability under threat - CXL Type 3 Vulnerability Assessment(ITESO, 2024-07) Vite-López, Erick E.; Gradilla-Negrete, Ramón E.The growing demand for data processing, driven by technologies such as artificial intelligence, has led the industry to seek more efficient solutions. The Compute Express Link (CXL) protocol stands out as a promising option, offering high-speed, low-latency interconnections between the CPU and other devices, thereby improving resource management, and facilitating the scaling of data-intensive applications. A case study of how the availability of a system could be compromised through a DoS attack targeting the CXL protocol is presented. The context of this work is based on a controlled, secure, and dedicated environment for this research. At no point is a real system/server compromised, and the study is based on the Next Generation Intel® Xeon Server CPU and a CXL type 3 test card. Established in 2019 and publishing the first official specification of the CXL protocol, called CXL 1.0, in March 2020, The CXL Consortium is an open industry standards group established to create technical specifications that enable groundbreaking performance for new usage models, while also supporting an open ecosystem for data center accelerators and other high-speed enhancements. Considering that the protocol is relatively young compared to other protocols, such as PCIe (Peripheral Component Interconnect Express), the "threat modeling" methodology will be followed to identify vulnerabilities that could potentially compromise the system's availability.Ítem Design of a 12-bit Sigma Delta ADC in 45 nm CMOS technology(ITESO, 2024-11) Jiménez-González, Mario A.; Martínez-Guerrero, Esteban; Aguilera-Galicia, Cuauhtémoc R.This thesis presents a 12-bit ΣΔ ADC design on 45 nm CMOS technology for MEMS sensor applications. The design was performed using Virtuoso Cadence tools. The circuit is composed by a first-order ΣΔ Modulator, a CIC filter, and a Decimator. The first-order ΣΔ Modulator having an oversampling ratio K=128 is developed implementing the switched-capacitor technique. The first-order ΣΔ Modulator is composed by an integrator, a comparator, and a 1-bit DAC. Simulation results show how the Modulator changes the output transitions frequency depending on the input voltage value, being K=128 the best tradeoff between the number of modulations and circuit complexity. The physical design of this block is fully customized. For the digital filter and decimator blocks, a third-order Cascaded Integrator Comb (CIC) filter is developed as a Verilog macro model to test and measure the transient and spectral response of the ADC, as well as its main Figures of Merit.Ítem Plataforma óptica experimental Tosa Rosa(ITESO, 2024-09) Castro-Alba, Raymundo; Pardiñas-Mir, Jorge A.Este trabajo de obtención de grado presenta el marco que he desarrollado para la formación de ingenieros de análisis de fallas y personal técnico en el tema de las comunicaciones ópticas, con el objetivo de apoyar el análisis del funcionamiento y las fallas presentes en dispositivos de transmisión y recepción óptica, área de trabajo de la empresa en donde laboro. El trabajo está dividido en dos: la descripción de los principios de las comunicaciones ópticas y el desarrollo y uso de una plataforma experimental. La primera parte describe los elementos más relevantes para el contexto del trabajo de análisis de funcionamiento y fallas en módems ópticos: Redes y Módems Ópticos, Fundamentos de Óptica, Láser y Fotodetectores PIN-APD, Fibras Ópticas, Transmisores Ópticos y Receptores Ópticos. La segunda parte describe la plataforma experimental, la cual es un sistema mínimo de comunicaciones ópticas que contiene un transmisor TOSA (Transmitter Optical SubAssembly), un receptor ROSA (Receiver Optical SubAssembly), y la fibra óptica como medio de transmisión. Con la plataforma óptica se pueden entender varios elementos de un módem óptico como son: El láser, los diodos PIN, la fibra óptica y el acondicionamiento de señal. La capacitación, objetivo de las evidencias presentadas en este trabajo, ha sido impartida a técnicos e ingenieros y se han obtenido buenos resultados en relación con la reducción de un bonepile (conjunto de tarjetas electrónicas con fallas funcionales) de 15 millones a 2 millones de dólares.Ítem RISC-V Floating Point Unit(ITESO, 2024-09) Alfaro-Gómez, Ricardo A.; Alvarado-Lagunes, Julián; Longoria-Gándara, Omar H.; Pizano-Escalante, José L.This document explores the representation and processing of arithmetic data, with a focus on Floating Point (FP) operations for RISC-V architecture. It introduces the IEEE 754 standard for FP representation, detailing its evolution and significance in achieving portability and reliability in hardware units. Challenges associated with FP operations, such as high storage and execution costs, are addressed, necessitating dedicated Floating Point Units (FPUs) to optimize performance. The document proposes the implementation of an FPU for RISC-V architecture as a means to align with industry standards and contribute to scientific advancements. It discusses various number representations, the IEEE FP standard, and the role of FPUs within processor designs. Additionally, it outlines the problem statement, objectives, and expected impact of FPU implementation, providing insights into the division and square root algorithms used for FPU implementation. Overall, this document provides a comprehensive overview of FP operations, the IEEE 754 standard, FPU implementation challenges, and the significance of RISC-V architecture in contemporary computing.Ítem Compute Express Link Optimization for Low Latency(ITESO, 2024-05) Baltazar-Ortiz, Ángel A.; Rangel-Patiño, Franciso E.This thesis delves into the architecture of the Compute Express Link® (CXL®) 1.1 specification, which is built on top of the physical and electrical interface of the peripheral component interconnect express® (PCIe®) Gen 5. CXL is a technology focused on efficiently handling generative artificial intelligence (AI) and its enormous memory performance demands. CXL enables coherency between the central processing unit (CPU) memory space and memory connected under devices for memory pooling. As CXL technology gains traction, optimizing latency has become a significant area for improvement. Fortunately, new configurations are available that can improve the user experience for advanced workloads. One way to reduce latency is to use the equalization process in fixed mode during CXL link bring-up and avoid recoveries or retries under the link training state machine (LTSSM) setup that are continuously triggered due to the bit error. Some equalizers are subject to operate in dynamic mode and require real-time latency optimization. The purpose of this thesis is to demonstrate the advantages and disadvantages of different optimization methods using latency measurement tools that are applicable only on the CXL validation stage. The study also utilizes optimization techniques implemented in MATLAB to determine the minimum global solution of an objective function. This research suggests that creating tools that can monitor, analyze, and control the optimal CXL link latency can contribute and improve significantly to future CXL technology implementations.Ítem Smart Audio Equalizer(ITESO, 2024-02) Teyssier-Ramírez, Luis A.; Longoria-Gándara, Omar H.En la actualidad, las personas suelen escuchar música en diferentes dispositivos, tales como teléfonos inteligentes, altavoces portátiles o sistemas de infotenimiento en automóviles. Sin embargo, algunas desconocen que estos dispositivos ya vienen equipados con ecualizadores de audio integrados, mientras que otros no saben cómo ajustarlos para obtener la mejor calidad de audio y mejorar la experiencia auditiva. En este proyecto de tesis, se propone una forma inteligente de ecualización de audio mediante inteligencia artificial. Se aplican automáticamente configuraciones preestablecidas de ecualización según el género musical que es determinado por un algoritmo. Se analizaron y compararon dos tipos de ecualizadores. Luego, se creó una aplicación en Matlab como prueba de concepto para demostrar las ventajas de estos ecualizadores y para implementar un proceso de etiquetado automático que utiliza técnicas de Recuperación de Información Musical (MIR) y un modelo de Red Neuronal Convolucional (CNN) incluido en la biblioteca Essentia. Los resultados del etiquetado se analizaron y discutieron para evaluar el rendimiento del modelo de aprendizaje profundo de Essentia, que se incorporó en la aplicación. En el futuro, este modelo podría entrenarse con diferentes conjuntos de datos que incluyan más géneros musicales, lo que mejoraría su funcionalidad. Además, podría implementarse en un dispositivo integrado utilizando soluciones de código abierto como Android Auto, para emular un sistema integrado como el de un sistema de infotenimiento en un automóvil.Ítem Application-Specific Integrated Circuit of an Inter-IC Sound Digital Filter for Audio Systems(ITESO, 2024-02) Dávila-Velarde, René S.; Longoria-Gándara, Omar H.Ítem Transitioning to a High-Performance Team that Possesses Advanced Technical Skills(ITESO, 2023-10) Pérez-Hernández, Paul; Longoria-Gándara, Omar H.Ítem Pluggable Fan Controller(ITESO, 2023-10) Bernal-Quintero, Carlos L.; Longoria-Gándara, Omar H.Ítem Post-Silicon Functional Validation of a DDR5 Memory Controller(ITESO, 2023-10) Hernández-Reyes, Federico J.; Longoria-Gándara, Omar H.Ítem Plataforma de info-entretenimiento basado en Android Automotive PIE 9(ITESO, 2023-06) Gutiérrez-Tirado, José A.; López-Flores, Juan E.; Santos-Lechuga, Isidro; Huidobro-García, Víctor H.Ítem Reporte de formación complementaria en área de concentración en diseño electrónico de alta frecuencia(ITESO, 2023-09) Cantor-González, José M.; Longoria-Gándara, Omar H.Ítem Optimization of Electrical Validation and Debug Time in Reference Clocks(ITESO, 2023-06) Arredondo-Sandoval, Luis E.; Salim-Maza, ManuelÍtem Mitigating Impedance Matching Disturbances of a Long-Range Wireless Transceiver with Classical Optimization Methods(ITESO, 2021-12) Coria-Pérez, Natalia; DelRey-Acuña, Juan R.Ítem Formación técnica complementaria y proyectos de impacto. Diseño electrónico en alta frecuencia(ITESO, 2016-01) Moreyra-González, Rogelio A.; Rayas-Sánchez, José E.Ítem PAM4 Transmitter and Receiver Equalizers Optimization for High-Speed Serial Links(ITESO, 2021-10) Ruiz-Urbina, Roberto J.; Rangel-Patiño, Francisco E.